Quad Lane 5Gbps PCIe 2.0 PHY IP (Silicon Proven in TSMC 22ULP/ULL)
The PCIe2.0 PHY IP transceiver is optimized for low power consumption.
The PCIe2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, built-in self test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs
View Quad Lane 5Gbps PCIe 2.0 PHY IP (Silicon Proven in TSMC 22ULP/ULL) full description to...
- see the entire Quad Lane 5Gbps PCIe 2.0 PHY IP (Silicon Proven in TSMC 22ULP/ULL) datasheet
- get in contact with Quad Lane 5Gbps PCIe 2.0 PHY IP (Silicon Proven in TSMC 22ULP/ULL) Supplier