The Quad SPI-3 to SPI-4 Bridge Intellectual Property (IP) Core targets the programmable array section of the ORCA ORSPI4 FPSC and provides the Link Layer bridging function between one to four SPI-3 links and a SPI-4 link.
- Complete Quad SPI-3 to SPI-4 Link Layer Bridge Solution Based on the ORCA ORSPI4 FPSC
- IP Targeted to the ORSPI4 Programmable Array Section. Implements Functionality Conforming to OIF-SPI3-01.0, Including:
- Up to four full-featured SPI-3 link interfaces
- Up to eight ports supported per interface.
- Parameterizable Byte or Packet Mode selection
- Configurable through the MicroProcessor Inter-face (MPI) ORCA 4 System Bus
- Programmable parity type on SPI-3 bus
- SPI-4 Functionality Supported by the Embedded Section of the ORSPI4, Including:
- Standard 10Gbps physical to Link Layer interface
- Support for "static" and "dynamic" alignment at the receive interface
- Single-link and multi-link operation
- SPI-4.2 transmit data protocol support logic
- Embedded calender-based sequence port polling mechanism and bandwidth allocation for 256 ports
Block Diagram of the Quad SPI-3 to SPI-4 Link Layer Bridge