The Quad Serial Peripheral Interface (OSPI) core is a serial data link (SPI) master which controls an external serial FLASH device.
Reading and writing the core is done on the AMBA® AHB bus interface. The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Dual, r Quad Bus modes.
The OSPI is compatible with various industry-standard DMA controllers. DMA operation in the OSPI can be enabled to assist a DMA controller in the loading (writing) of the transmit FIFO, and the unloading (reading) of the receive FIFO.
The Execute in Place (XIP) Mode allows an AHB Master to directly read the contents of any of several industry-standard FLASH devices (such as Winbond, Macronix, Spansion and Micron devices) simply by reading from the address space of the QSPI Controller.
- 4-bit to 32-bit serial transmit & receive
- Full and half duplex modes
- Software programmable Master or Slave mode
- Software programmable SCLK rate for Master mode
- Quad-bit mode operation
- Dual-bit mode operation
- 64-word Tx and Rx FIFOs
- Asynchronous Slave Interface
- AMBA AHB interface
- Interrupt control
- LSB or MSB mode
- Up to 4 slaves under Master control
- DMA Interface
- Compatible with many industry-standard FLASH devices
- Execute-in-place (XIP) functionality for industry standard FLASH devices
- Verilog Source
- Complete Test Environment
- AHB Bus Functional Model
- C-Sample Code
Block Diagram of the Quad SPI Controller with Execute in Place AHB/APB/AXI