NetTimeLogic’s DCF Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other nodes via DCF signal encoded as PWM over a cable. The core encodes the time in the same format as the DCF77 sender, so it is compatible with DCF77 nodes which use the PWM encoded DCLS signal (which is what comes normaly from a DCF77 receiver). The whole encoding, conversion, algorithms and calculations are implemented in the core, no CPU is required. This allows running IRIG synchronization completely independent and standalone from the user application. The core can be configured either by signals or by an AXI4Light-Slave Register interface.
All calculations and corrections are implemented completely in HW.