Comcores Fast Fourier Transform (FFT) IP core is an implementation of a Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the Discrete Fourier Transform (DFT). The FFT uses a Radix-2,
Decimation-In-Time (DIT) and in-place architecture which improves overall efficiency of the computation in terms of speed while keeping the digital footprint at a minimum. The core comes with a large variety of run-time configurations such as FFT/IFFT mode, transform size, ordering of outputs and Cyclic Prefix insertion which makes it suitable for a large variety of applications such as OFDM systems and real-time signal analysis.
The FFT IP also comes as a dual core version where the total execution time of the algorithm is halved at the cost of a slightly larger digital footprint. For any application the FFT IP core delivers on your need for speed and performance whether the target is FPGA or ASIC.
- Delivers Performance
- Supports both FFT and IFFT transformation
- Uses a Cooley-Tukey decimation in time algorithm with radix-2 sizes and in-place computations
- Fixed-point arithmetic
- Complex input and output
- Option for a dual core version for ultra low transformation execution time Highly Configurable
- Configurable for many operating modes
- Support both FFT and IFFT computations
- Run-time configurable transform lengths of size 8 – 65535
- Run-time configurable scaling of data at several points during computation
- Normal or natural order on outputs
- Supports Cyclic Prefix insertion
- Single RTL code base supports all configurations
- Easy to use
- Simple configuration signals for run-time configurations and enabling/disabling of features
- Simple test bench is included
- Silicon Agnostic
- Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
Block Diagram of the Radix-2 FFT IP Core