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RAM-based Shift Register
The Xilinx LogiCORE™ RAM-based Shift Register IP core generates fast, compact FIFO-like-style registers, delay lines or time-skew buffers using the SRL16/SRL32 mode of the slice LUTs available in Xilinx FPGA devices. Implementing Shift Registers with the SRL16/SRL32 provides large resource and power savings. The IP supports fixed-length or variable-length shift registers.
Features
- Supports inputs ranging from 1 to 256 bits wide
- Supports shift register depth from 1 to 1088 for fixed-length or 1 to 1024 for variable-length sift registers.
- Speed or resource optimization for all modes with capability to specify optional output register.
- Instantaneous Resource Estimation
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