The RapidIO to AXI Bridge is a highly flexible and configurable IP used along with the native RapidIO Controller (GRIO) to provide RapidIO interface on one side and AXI interface on the system side. The Bridge has been architectured to interface with a RapidIO controller used as a Host or device. The RIO-AXI BRIDGE uses high speed multi-channel DMA and Message controllers to match the bandwidth requirements of the RIO solution.
The RapidIO to AXI Bridge is a simple, configurable and layered architecture, independent of applications, implementation tools or target technology. The controller architecture is carefully tailored to optimize latency, power consumption, and silicon footprint, making it ideal for cost and performance sensitive applications. The RapidIO to AXI Bridge provides highly scalable bandwidth through a configurable data path width and clock frequency.
The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology. Mobiveil solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally. Its flexible backend interface makes it easy to be integrated into wide range of applications. Mobiveil solution provides highly scalable bandwidth through configurable lanes, widths and frequencies.
- Compliant with RapidIO specification, Revision 4.0
- Compliant to AMBA AXI protocol v4
- Supports 32-bit or 38-bit addressing
- AXI PIO operation with configurable number of AXI Slaves
- RapidIO PIO operation with configurable number of AXI Masters
- Multi-channel Read and Write DMA
- Register based and descriptor based modes of DMA
- Interrupt generation to both AXI and RapidIO
- Inbound and Outbound Doorbell
- Logical Flow control
- Bypass Mode
- Software configurable address mapping between RapidIO and AXI systems
- CSR registers optional access through APB
- Inbound and Outbound Mailbox Support
- Data streaming support
- Supports 64 and 128 bit Datapath
- To build a full-system solution the Mobiveil partner eco-system provides access to additional components such as verification IP, PHYs and related design services.
- Verilog RTL
- Behavioral test bench and test cases
- PCI Express and Application BFM
- ASIC Synthesis environment
- Wireless Base station
- Satellite Communications
Block Diagram of the RapidIO to AXI Bridge