Compact, ultra-low power ARC EM processors and ASIL-Ready ARC EM Safety Island IP feature excellent code density
An ECC code word must be calculated over an entire data word. Misaligned bursts can have partial data words at the front and back end of the burst. To calculate the correct ECC code word, the Read-Modify-Write Core forms the correct starting and ending data words by reading the existing data words and combining them appropriately with the new partial data words.
The core performs address translation from byte addressing to the 64-bit or 128-bit addressing of the memory devices.
The core is provided with the Multi-Burst Core enabling it automatically break long burst requests into multiple requests matching the memory’s native burst length
Read-Modify-Write write operations are by their nature inefficient. The Read-Modify-Write Core implements a prefetch architecture that maximizes the memory bus utilization as efficiently as possible.
The core is compatible with memory modules that don’t provide Data Mask lines.
Rambus also provides IP Core customization services. Contact Rambus for a quote.
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