Secantec, Inc. RS Code is highly optimized implementation. The Code is ultra-low latency, low gate count and low power.
It is observed that 99.5% of the traffic is without errors and 0.5% has errors. For traffic without errors there is no latency introduced by the code in encoder or decoder. For 0.5% with errors error correction will introduce latency. With the new techniques this latency is also reduced to zero clocks, though there will be some combinatorial delay through logic gates. For 99.5% of the traffic without errors this delay is a lot lesser .
The IP includes
-- Generator polynomial RTL
Decoder consists of following blocks
-- Syndrome Calculator
-- Phi Calculator circuitry for erasures
-- BerlekampMassy Circuitry
-- Chien Search
-- Forney Algorithm
If RS is configured for 16 bits of error correction, then the same decoder/encoder can be used for any number of bit corrections from 1 to 15
This way the overhead can be reduced if desired.