Adaptive Clock Generation Module for DVFS and Droop Response
Reed Solomon Encoder/Decoder
- The Reed Solomon Decoder receives an (N=K+2T) codeword, and it can locate and correct up to 8 possible symbol errors or up to 14 erasures.
-Both the Encoder and the Decoder support any input timing pattern, in case of the Encoder; the output timing pattern will be the same as the input. In case of the Decoder; the output timing pattern is fully controlled in order to support any desired pattern by the user.
- The Reed Solomon Decoder keeps track of corrected errors. Input codewords with more than 8 errors are regarded as uncorrectable, and are flagged.
-The Implementation of VK-301 Reed Solomon IP Core targets very low latency, high speed, and low gate count with a simple interface for easy integration on SoC applications.
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