CoreRSENC is an RTL generator that produces an Microsemi FPGA–optimized Reed-Solomon (RS) encoder core based on user-defined parameters. RS codes are a class of error-correcting codes used to detect and correct errors that might be introduced into digital data when it is transmitted or stored. Error-correcting codes incorporate redundancy in data. With this redundancy, only a subset of all possible transmissions contains valid messages. This means the valid codes are separated from each other so errors are not likely to corrupt one valid code into another. The encoded data can then be transmitted or stored.
* Parameterizable RS Encoder generator
* Supports arbitrary time intervals between the output code words, including zero interval
* Symbol widths from 3 to 8 bits
* Supports shortened code
* Supports any valid primitive polynomial for a given symbol width
* Supports CCSDS-16 and CCSDS-8 encoding
* In the CCSDS mode supports data encoding presented in conventional or dual basis
This core is available for FREE in Libero IDE Catalog.