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RISC-V 64-bit Processor
The NOEL-V is a synthesizable VHDL model of a 64-bit processor that implements the RISC-V architecture. The processor is the first released model in Cobham Gaisler's RiSC-V line of processors that complement the LEON line of processors.
The NOEL-V design shares elements with the high-performance LEON5 and introduces many improvements over the LEON4 pipeline.
The NOEL-V is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the Cobham Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
The NOEL-V design shares elements with the high-performance LEON5 and introduces many improvements over the LEON4 pipeline.
The NOEL-V is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the Cobham Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
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RISC-V IP
- RISC-V processor - 32 bit, 5-stage pipeline
- 64-bit RISC-V application processor core with 7-stage pipeline
- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers
- 64-bit RISC-V application processor core with L2 cache coherence
- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 16 registers
- Dual-issue, 64-bit RISC-V application processor core with 7-stage pipeline