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RISC-V 64-bit Processor
The NOEL-V is a synthesizable VHDL model of a 64-bit processor that implements the RISC-V architecture. The processor is the first released model in Cobham Gaisler's RiSC-V line of processors that complement the LEON line of processors.
The NOEL-V design shares elements with the high-performance LEON5 and introduces many improvements over the LEON4 pipeline.
The NOEL-V is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the Cobham Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
The NOEL-V design shares elements with the high-performance LEON5 and introduces many improvements over the LEON4 pipeline.
The NOEL-V is interfaced using the AMBA 2.0 AHB bus and supports the IP core plug&play method provided in the Cobham Gaisler IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
Features
- RISC-V 64IMC, with AFDN (ie GCN) to be released
- 64-bit architecture
- Hardware multiply and divide units
- Compressed (16 bit) instruction support
- Machine, supervisor and user mode
- RISC-V standard PLIC
- RISC-V standard PMP (physical memory protection)
- RISC-V standard external debug support
- Advanced 7-stage dual-issue in-order pipeline
- Dynamic branch prediction, branch target buffer and return address stack
- Four full ALUs, two of them late in the pipeline to reduce stalls
- Separate instruction and data L1 cache (Harvard architecture) with snooping
- Configurable L2 cache: 256-bit internal, 1-4 ways, 16 KiB - 8 MiB
- AMBA 2.0 AHB bus interface, 64- or 128-bit wide
- Robust and fully synchronous single-edge clock design
- Extensively configurable
- Large range of software tools: compilers, kernels and debug monitors
- High performance: 4.36 CoreMark/MHz
- The NOEL-V processor model is being continuously extended with the first features to be released during the fist half of 2020:
- RISC-V standard MMU with configurable TLB
- Atomic instruction extension
- 32/64 bit floating point extensions using a high-performance fully pipelined IEEE-754 FPU
- User level interrupts
- Power-down mode and clock gating
- Hypervisor support
- Symmetric Multiprocessing (SMP) support
View RISC-V 64-bit Processor full description to...
- see the entire RISC-V 64-bit Processor datasheet
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RISC-V IP
- High performance Linux-capable processor
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- Low-power 32-bit RISC-V processor
- Compact RISC-V Processor - 32 bit, 3-stage
- RISC-V processor - 32 bit, 5-stage pipeline
- Compact, efficient 64-bit RISC-V processor with 5-stage pipeline