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RISC-V 64-bit Standard CPU
The NS 72 supports the RV64GCV instruction set and is an application CPU supporting a variety of operating systems, while maintaining Akaria’s functional safety features. Multi-core processing and the optional RISC-V Vector Extension v 1.0 Vector Processor Unit enable multi-tasking and data-parallel high-performance computing.
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Block Diagram of the RISC-V 64-bit Standard CPU IP Core
RISC-V IP
- TESIC CC EAL5+ Secure Element IP Core
- TESIC RISC-V CC EAL5+ Secure Element Soft/Hard Macro
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP
- High performance dual-issue, out-of-order, 7-stage pipeline superscalar core
- Single-issue, in-order, 3-stage pipeline and RISC-V compatible MCU-class core, Ultra-low power RISC-V microcontroller