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RISC-V-based SoC template
IOb-SoC is a RISC-V SoC template written in Verilog, which users can download for free, modify, simulate and implement in FPGA or ASIC. It supports stand-alone and booting modes, and can use internal RAM or an external DDR controller via L1/L2 cache systems.
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Block Diagram of the RISC-V-based SoC template IP Core
RISC-V IP
- Intelligent Sensor and Power Management Design Platform
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- Low-power 32-bit RISC-V processor
- Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
- 64-bit RISC-V application processor core with 7-stage pipeline
- High performance Linux capable vector processor