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1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
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RISC-V debug solutions
RISC-V is an open source instruction set architecture developed by UC Berkeley and now being widely adopted throughout the industry. As a member of RISC-V International, Embedded Analytics has played a leading role in defining and implementing the debug and processor trace architecture for RISC-V.
Our RISC-V debug solution conforms to industry standards and scales to suit any requirement. If you're developing a cost-sensitive uni-processor chip – for an IoT application, for example – you can use our IP to implement straightforward standards-compliant run-control and JTAG connectivity, supported by our Eclipse-based IDE. At the other end of the complexity spectrum, you can choose a system capable of delivering wire-speed trace and rich information about the operation of even the largest system-level SoC, with multiple CPUs.
Our RISC-V debug solution conforms to industry standards and scales to suit any requirement. If you're developing a cost-sensitive uni-processor chip – for an IoT application, for example – you can use our IP to implement straightforward standards-compliant run-control and JTAG connectivity, supported by our Eclipse-based IDE. At the other end of the complexity spectrum, you can choose a system capable of delivering wire-speed trace and rich information about the operation of even the largest system-level SoC, with multiple CPUs.
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RISC-V IP
- RISC-V processor - 32 bit, 5-stage pipeline
- 64-bit RISC-V application processor core with 7-stage pipeline
- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers
- 64-bit RISC-V application processor core with L2 cache coherence
- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 16 registers
- Dual-issue, 64-bit RISC-V application processor core with 7-stage pipeline