Codasip-Bk5 delivers high embedded performance with RISC-V instruction-set compatibility, allowing users to leverage the rich ecosystem of software and tools becoming available, in addition to those provided by Codasip.
Codasip-Bk5 can be used with standard peripherals allowing development using RTOSs ported to RISC-V including such as FreeRTOS.
For licensees who also license the Studio tools, it is possible to add custom instructions and to add other features to the Bk5.
- Support for RV32IM
- 5-stage pipeline
- Thirty-two 32-bit general purpose registers
- Optional compact instruction extensions (“C”)
- Optional floating point extensions (“F”)
- Optional instruction pre-fetch
- Optional instruction and data cache
- Interrupt support
- JTAG debug
- < 0.10mm² in 40LP
- From about 36 kgates for integer core
- From about 67 kgates for core with floating point
Block Diagram of the RISC-V processor - 32 bit, 5-stage IP Core