The Bk5 is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requirements. The core has a 5-stage pipeline and is offered in two versions.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip Bk cores, it is possible to create custom instructions using Codasip Studio to extend the Bk5 and to generate corresponding hardware and software development kits.
- 32-bit RISC-V core
- Available in two versions:
- Fully parallel multiplier
- 5-stage pipeline
- Dynamic Branch Predictor
- RISC-V mode support:
- Internal interrupt controller
- Optional FPU
- Optional instruction and data tightly coupled memories (TCM)
- Optional 8 or 16 PMP regions
- Optional L1 data and instruction caches
- On-chip debugger
- JTAG and RISC-V Debug module
- Wide choice of configuration options.
- Ability to create custom RISC-V extensions to optimise performance
- Efficient architectural exploration of custom extensions with Studio
- Automatic HDK and SDK generation from Studio
- Rigorous verification of modified Bk5 core using UVM
- Human-readable and structured RTL in either:
- System Verilog
- Hardware development kit (HDK)
- Synthesis scripts
- Simulation testbenches
- Debug support
- Software development kit (SDK)
- LLVM C-compiler
- Instruction-accurate simulator
- Cycle-accurate simulator
- Option for extending Bk5
- CodAL model for Codasip Studio
- Full-feature Studio tool for extending Bk5 core
- GUI for rapid development and debugging
- Automatic HDK & SDK generation
- The Bk5 core is suitable for embedded applications requiring medium processing performance and a higher clock frequency.
Block Diagram of the RISC-V processor - 32 bit, 5-stage IP Core