Codasip-Bk5 delivers high embedded performance with RISC-V instruction-set compatibility, allowing users to leverage the rich ecosystem of software and tools becoming available, in addition to those provided by Codasip.
Codasip-Bk5 can be used with standard peripherals allowing development using RTOSs ported to RISC-V including such as FreeRTOS.
For licensees who also license the Studio tools, it is possible to add custom instructions and to add other features to the Bk5.
- Support for RV32IM
- 5-stage pipeline
- Thirty-two 32-bit general purpose registers
- Jump predictor
- Optional floating point extensions (“F”)
- Optional instruction and data cache
- Interrupt support
- JTAG debug
- From about 0.37mm² in 55 nm
- From about 33 kgates for integer core
- From about 63 kgates for core with floating point
- The Bk5 core is suitable for embedded applications requiring greater processing performance and a higher clock frequency.
Block Diagram of the RISC-V processor - 32 bit, 5-stage IP Core