English
You are here:
RISC-V processor - 32 bit, 5-stage pipeline
The Bk5 is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requirements. The core has a 5-stage pipeline and is offered in two versions.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip Bk cores, it is possible to create custom instructions using Codasip Studio to extend the Bk5 and to generate corresponding hardware and software development kits.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip Bk cores, it is possible to create custom instructions using Codasip Studio to extend the Bk5 and to generate corresponding hardware and software development kits.
Features
- 32-bit RISC-V core
- Available in two versions:
- RV32IMC
- RV32IMCF
- Fully parallel multiplier
- 5-stage pipeline
- Dynamic Branch Predictor
- RISC-V privilege mode support:
- Machine, User
- Internal interrupt controller
- Up to 256 sources
- Optional FPU
- Optional instruction and data tightly coupled memories (TCM)
- Optional 8 or 16 PMP regions
- Optional L1 data and instruction caches
- On-chip debugger
- JTAG and RISC-V Debug module
Benefits
- Flexibility
- Wide choice of configuration options.
- Extensibility
- Ability to create custom RISC-V extensions to optimise performance
- Efficient architectural exploration of custom extensions with Studio
- Automatic HDK and SDK generation from Studio
- Rigorous verification of modified Bk5 core using UVM
Deliverables
- Human-readable and structured RTL in either:
- Verilog
- VHDL
- System Verilog
- Hardware development kit (HDK)
- Synthesis scripts
- Simulation testbenches
- Debug support
- Software development kit (SDK)
- LLVM C-compiler
- Assembler
- Disassembler
- Linker
- Instruction-accurate simulator
- Cycle-accurate simulator
- Profiler
- Option for extending Bk5
- CodAL model for Codasip Studio
- Full-feature Studio tool for extending Bk5 core
- GUI for rapid development and debugging
- Automatic HDK & SDK generation
Applications
- The Bk5 core is suitable for embedded applications requiring medium processing performance and a higher clock frequency.
Block Diagram of the RISC-V processor - 32 bit, 5-stage pipeline
View RISC-V processor - 32 bit, 5-stage pipeline full description to...
- see the entire RISC-V processor - 32 bit, 5-stage pipeline datasheet
- get in contact with RISC-V processor - 32 bit, 5-stage pipeline Supplier
RISC-V IP
- High performance Linux-capable processor
- Digital and mixed-signal IP and ASIC RISC-V reference design for USB Type-C/PD power adapter/charger
- Low-power 32-bit RISC-V processor
- Compact RISC-V Processor - 32 bit, 3-stage
- Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
- Linux capable 64-bit RISC-V processor core with 7-stage pipeline