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RISC-V processor - 32 bit, 5-stage pipeline
The Bk5 is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requirements. The core has a 5-stage pipeline and is offered in two versions.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip Bk cores, it is possible to create custom instructions using Codasip Studio to extend the Bk5 and to generate corresponding hardware and software development kits.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip Bk cores, it is possible to create custom instructions using Codasip Studio to extend the Bk5 and to generate corresponding hardware and software development kits.
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