English
MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
You are here:
RISC-V Processor - RV12 - 32/64 bit, Single Core CPU
The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of the Roa Logic’s 32/64bit CPU family based on the industry standard RISC-V instruction set.
The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses. It features an optimizing folded 4-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.
Optional features include Branch Prediction, Instruction Cache, Data Cache, and Debug Unit. Parameterised and configurable features include the instruction and data interfaces, the branch-prediction-unit configuration, and the cache size, associativity, and replacement algorithms. Providing the user with trade offs between performance, power, and area to optimize the core for the application
The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses. It features an optimizing folded 4-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.
Optional features include Branch Prediction, Instruction Cache, Data Cache, and Debug Unit. Parameterised and configurable features include the instruction and data interfaces, the branch-prediction-unit configuration, and the cache size, associativity, and replacement algorithms. Providing the user with trade offs between performance, power, and area to optimize the core for the application
View RISC-V Processor - RV12 - 32/64 bit, Single Core CPU full description to...
- see the entire RISC-V Processor - RV12 - 32/64 bit, Single Core CPU datasheet
- get in contact with RISC-V Processor - RV12 - 32/64 bit, Single Core CPU Supplier
Block Diagram of the RISC-V Processor - RV12 - 32/64 bit, Single Core CPU
RISC-V Processor IP
- RISC-V processor - 32 bit, 5-stage pipeline
- 64-bit RISC-V application processor core with 7-stage pipeline
- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers
- 64-bit RISC-V application processor core with L2 cache coherence
- Compact RISC-V Processor - 32 bit, 3-stage pipeline, 16 registers
- Dual-issue, 64-bit RISC-V application processor core with 7-stage pipeline