The Bluetooth 4.0 Baseband Controller IP Core is compatible with "classic" BR/EDR Bluetooth and Bluetooth low energy specifications. Backward compatible with Bluetooth 2.1+EDR and 3.0, it is composed of a synthesizable Bluetooth hardware baseband core controller for integration into ASICs and FPGAs, driven by a portable and configurable firmware containing all protocol layers up to HCI.
The hardware baseband core controller, in charge of packet encoding/decoding and frame scheduling, is complemented by a CVSD hardware codec with a-law/u-law/linear PCM samples converter for voice applications. The firmware is composed of the BR/EDR Link Controller (LC), LE Link Layer (LL), Link Manager (LM) and Host Control Interface (HCI).
Compatible with the standard Bluetooth HCI, the Bluetooth 4.0 Baseband Controller can be used with any Bluetooth 4.0 host software protocol stack and profiles, either split around the HCI so that the lower layers and upper layers can run on different processors or systems, or combined together to run on the same processor to make a fully hosted solution. The customer is free to choose any 3rd party Bluetooth 4.0 compatible host protocol stack and profiles, including the open source BlueZ.
The firmware is provided with reference platform drivers and with a small scheduler (or kernel OS) which is a small and efficient Real Time Operating System (RTOS), offering task management, inter-task communications, message (queues and events) management and timing management.
The Bluetooth 4.0 Baseband Controller IP deliverable includes a hardware simulation test bench with regression test suit, synthesis scripts, and a user-friendly validation tool running under Window or Linux allowing easy unit testing and regression at system level.
- Bluetooth dual mode 4.2 compliant
- Backward compatible with Bluetooth 1.2, 2.0+EDR, 2.1+EDR and 3.0.
- Supports all BR, EDR and BLE packet types
- Support of scatternet modes in both BR/EDR and BLE links (master + slave simultaneous links, several simultaneous slave links)
- Adaptive Frequency Hopping (AFH) in piconet and scatternet operation for improved coexistence with WLAN devices
- Hardware encryption
- WLAN and broadband coexistence interfaces
- Sniff Sub-rating for optimized power consumption
- Secured Simple pairing for improved user experience
- Extended Inquiry Response for faster connection
- Encryption Pause and Resume
- Enhanced power control
- Designed in synthesizable RTL for easy technology migration for the hardware portion, and in C for the software portion
- Low gate count and low memory footprint
- Designed for minimal power consumption
- Support of 32000 Hz and 32768 Hz low power clock (can be used for hold, park and sniff)
- Low operating frequency dynamically selectable between 13 and 32 MHz. Other frequencies can be supported on request
- Bluetooth clock and multiple offsets management for scatternet operation in master and slave devices
- Optimized for use with RivieraWaves Bluetooth RF IP. Other RF can be supported on request
- Direct voice bus from CVSD codec, with support of up to 2 voice channels
- AMBA2 AHB/APB bus for easy integration into ARM based platforms
- Developped and validated on 32-bit processor. Can support any 32-bit processor (ARM Cortex M3, Cortus APS3, ARC605, etc.)
- DFT ready, accepted by major ATPG tools
- Supplied with compilation, simulation and synthesis scripts
- Supplied with hardware test bench and test suite permitting regression of the core after user edits
- Supplied with a user-friendly validation tool running under Windows or Linux allowing easy unit testing and regression at system level
- Comprehensive documentation and training
- hardware: Verilog RTL, testbench, compilation, simulation and synthesis scripts
- software: C
- test tool running on Windows or Linux
- smart phones
- ear buds, headsets, speakers
- remote control
Block Diagram of the Bluetooth 4.0 Baseband Controller IP Core