1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
RLDRAM Controller MACO Core
The RLDRAM controller is designed to support RLDRAM I with target speeds up to 300 MHz DDR and RLDRAM II CIO or SIO modes with target speeds up to 400 MHz DDR.
Note the RLDRAM IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array. Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.
Software Requirements
* ispLEVER version 7.0 or later
* MACO design kit
* MACO license file
View RLDRAM Controller MACO Core full description to...
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Block Diagram of the RLDRAM Controller MACO Core IP Core
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