RLDRAM Controller MACO Core
The RLDRAM controller is designed to support RLDRAM I with target speeds up to 300 MHz DDR and RLDRAM II CIO or SIO modes with target speeds up to 400 MHz DDR.
Note the RLDRAM IP Core is implemented using both MACO ASIC gates and soft logic in the FPGA array. Since a significant portion of the implementation is in MACO, more of the FPGA Array is left for the user.
Software Requirements
* ispLEVER version 7.0 or later
* MACO design kit
* MACO license file
View RLDRAM Controller MACO Core full description to...
- see the entire RLDRAM Controller MACO Core datasheet
- get in contact with RLDRAM Controller MACO Core Supplier
Block Diagram of the RLDRAM Controller MACO Core IP Core

FPGA IP
- Ethernet Switch / Router IP Core - Efficient and Massively Customizable
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Audio Weaver - Audio Algorithm Generator tool (Design, Develop, Deploy)
- Embedded FPGA cores in TSMC 22ULP/28HPC/HPC+
- Embedded FPGA
- USB3.0 DR-OTG Controller IP Core