ROM Compiler IP, UMC 90nm CIS process

UMC 90nm CMOS Image Sensor process 1P3M Via ROM compiler.

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Memory

DDR4 Memory Controller
DDR4/DDR3 Memory Controller
LPDDR2/LPDDR1 Memory Controller
LPDDR2/DDR3 Memory Controller
LPDDR3/LPDDR2 Memory Controller
The SST SuperFlash® IP is an embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability.

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