Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”.
The operations necessary for the RSA cannot be efficiently implemented on an embedded CPU, however, typically requiring many seconds of the CPU time for signature verification.
RSA1-E implements by far the most time-consuming operation of the RSA cryptography: so called “exponentiation” to enable low-power operation of the battery-powered devices.
The design is fully synchronous and available in multiple configurations varying in bus widths, set of finite fields supported and throughput.
- Small size: RSA1-E starts from less than 10K ASIC gates (intermediate result storage memory required; size depends on the core configuration)
- Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications
- Support for RSA binary fields of configurable bit sizes up to 2048
- Microprocessor-friendly interface
- Test bench provided
- Synthesizable Verilog RTL source code
- Software modules for a complete RSA implementation (optional)
- Verilog testbench (self-checking)
- Software modules test harness
- Vectors for testbench and harness
- Expected results
- User Documentation
- Secure communications systems
- Implantable medical devices
- Digital Rights Management (DRM) for battery powered electronics
- Digital Signature using Reversible Public Key (rDSA) standard ANSI X9.31
- Digital Signature Standard (DSS) FIPS-186
- PKCS RSA cryptography per RFC 2347
Block Diagram of the RSA Public Key Exponentiation Accelerator IP Core