The MVD RTP Receiver allows the reception and the processing of an RTP stream.
The RTP receiver stores the incoming RTP packets into an external memory (for example in DDR3). During RTP packet reception, the RTP receiver analyses the different fields of the incoming RTP packet and reorder (if necessary) the incoming packet in the external memory. After the receiver has stored sufficient number of RTP packets (depending on RTP payload length), the RTP receiver will present the valid data on the output bus .
As the accepted payload is only MPEG2-TS, the used Timestamp clock value is only 90kHz. An efficient compensation for the clock value 90kHz is implemented inside the RTP Receiver which permits to compensate the clock drift (±100 ppm).
- Drop-in module for Spartan™-6, Virtex™-7, Artix™-7, Kintex™-7 and Zynq™ Xilinx FPGAs
- Possibility to bypass RTP de-encapsulation to perform simple UDP de-encapsulation
- External Memory is mandatory for buffering incoming RTP packets to absorb network jitter, packets loss and packets disorder
- 8MB Memory is required by RTP Receiver
- TS Payload only supported (for more Payload type please contact MVD)
- Usable in routed network with an efficient dejittering due to the field TIMESTAMP of RTP packets
- Clock compensation for 90kHz (Clock value for TIMESTAMP Transport Stream) ±100 ppm
- Efficient packet reordering (for packet loss and packet disorder)
- Netlist version available for ISE and VIVADO
- Netlist for core generation
- VHDL top file
- VHDL source code : can be delivered as an option under NDA and other specific clauses
- MVD RTP receiver can be used to receive UDP/RTP packets (or UDP packets only) on an Ethernet Network.
- It may be used to receive IPTV UDP/RTP compliant stream in applications related to Multimedia transport.
Block Diagram of the RTP Receiver IP Core