This RTP Transmitter IP core implements a full Hardware RTP Transmitter.
If several channel are implemented into the FPGA, it allows sending RTP packets with a different payload type and different length on each channel.
MVD UDP/IP Stack IP core is mandatory to use this core.
- Drop-in module for Spartan™-6, Virtex™-7, Artix™-7, Kintex™-7 and Zynq™ Xilinx FPGAs
- Companion core of the MVD UDP/IP Stack IP core
- RTPv2 encapsulation
- Various Payload Type supported
- Support FEC Transmitter (optional)
- Variable RTP packet Payload length
- Computation of RTP Timestamp for RTP packets
- Possibility to bypass RTP Encapsulation to perform simple UDP Encapsulation for application which requires only UDP transmissions
- UDP compatible input
- Programmable Parameters of RTP and FEC (CPU interface)
- 2D-FEC transmitter support (option) compliant with SMPTE 2022 only for MPEG-TS (Payload type 33)
- FEC option requires external memory
- Netlist version available for ISE and VIVADO
- Netlist for core generation
- VHDL top file
- VHDL source code: can be delivered as an option under NDA and other specific clauses
- MVD RTP transmitter is specially developed to transmit RTP flows on a routed network. It can be used to send IPTV compliant streams.
Block Diagram of the RTP Transmitter IP Core