Complex Decimation is a fundamental piece of any rx radio chain. The MLD211 is a high performance integer decimator that offers a high degree of configurability.
Proven to work with clock speeds up to 200Mhz, this device can handle sample up to (2^m)*200MSamp/s where 2^m is the quantity of samples processed per clock cycle
Inputs and outputs are highly adjustable with parameters to fit your designs to ease integration. Change many parameters at compile time to chose your own trade offs.
- Paramaterized N sample per clock processing
- Paramaterized CIC order
- Paramaterized data I/O size
- Paramaterized flop stages
- Increase parallelization to reduce fdev
- Decide how many stages are required to fit your system’s need
- Easy integration with flexible I/O
- -High performance
- -User gets to chose what performance/area tradeoff is best for their application
- Verilog Source code
- Instantiation Example
- RF, Wireless, DDC, DDU, ADC interface, DAC interface, MODEM, QPSK, QAM, Signal Generation, Signal Mixing, Radio Chain