L&TTS SATA AHCI controller is a highly configurable core and implements the SATA Host bus adaptor that can be interfaced with standard third party SATA PHY. The core leverages GDA's design expertise from its high speed interconnect family of IP's including USB 3.0, SSIC, Unipro, UFS.
The SATA AHCI Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings when used in laptop and power-sensitive embedded systems.
The controller exposes a high performance system interface such as AXI/PCIe for use in servers and high end storage networks or an area optimized system interface such as AHB for use in embedded systems.
The controller's simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.
GDA solution allows the licensees to easily migrate among FPGA, Gate array and Standard cell technologies optimally
- Compliant with SATA 3.0 and AHCI 1.3 Standards
- Supports all generation of SATA Devices – Gen 1, Gen 2, Gen3 (1.5, 3.0 and 6.0 Gbps data rates, respectively)
- Support DMA and PIO protocols
- Supports all HBA Capabilities
- Supports Native command Queueing
- Supports Hot-plug feature.
- 32 Command Slots per port
- Supports Command Completion Coalescing
- Aggressive Link Power Management
- Auto-generating Partial-Slumber state transitions when no commands available for processing.
- Command and FIS based switching
- Fully programmable FIS content.
- Includes support for BIOS/OS Handoff
- Supports Multiple DRQ block data transfers for PIO command protocol
- Supports up to 32 ports
- Datapath Width : 32/64 bits; PHY Interface : 8/16/32-bit
- Master Interface for system access : AHB/AXI
- Slave Interface for Register access : AHB/PBUS
- Configurable FIFOs
- Support for port multipliers.
- Highly modular and configurable design
- Clearly demarked clock domains
- Extensive clock gating support
- Multiple Power Well Support
- Software control for key features
- Multiple loop backs for debug
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- Design Guide
- Verification Guide
- Synthesis Guide