SATA 3 HOST IP on ARRIA 10 FPGA

Features

• Rate Match FIFO
• - Manage SATA reference frequency difference between the FPGA and the Disk
• Physical Layer features
• - Detect OOB and COMWAKE
• - Detect the K28.5 comma character and provide a 32 bit parallel output
• - Power management mode handled by state machine (shared between Phy and Link layer)
• - Provides error indication to upper layers
• - 8b/10b encoding and decoding
• - Fixed Speed 6Gbs, 3Gbs or 1.5Gbs
• Link Layer features
• - Scrambling of TX data and descrambling of RX data
• - CRC 32 calculation and check
• - Report transmission status and error to Transport Layer
• - Enable BIST Retimed loopback and pattern generation modes
• - Auto inserted hold primitive to avoid FIFO overflow and underflow
• - Partial and slumber power management modes
• - The interface between the link layer and the transport layer is 32-bit wide
• Transport Layer features
• - 48-bits sector address
• - Programmed IO (PIO) and DMA modes
• - Support BIST FIS transmission and reception
• - Automatic error FIS retry capability
• - Implement Shadow Registers and SATA SuperSet registers
• - Simple synchronous CPU and DMA Interface for data transfers including DMA hold-off capability
• - DMA interface can be connected easily to memory space or FIFOs
• - 128-Word Ingress and Egress FIFO between Transport and Link Layer
• - NCQ Support

Block Diagram of the SATA 3 HOST IP on ARRIA 10 FPGA

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