SATA 6G PHY in SMIC (40nm, 28nm)
The PHY includes a wide range of test capabilities including built-in per-channel BERTs, flexible fixed and random pattern generation, error counting on patterns or disparity, digital phase or voltage margining (bathtub curves), and built-in per channel scopes. The high-margin, robust SATA PHY architecture tolerates for manufacturing variations such as process, voltage and temperature. The SATA PHY passed interoperability testing utilizing industry-leading 65-nm, 40-nm, and 28-nm process technologies.
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