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SATA 6G PHY in UMC (40nm, 28nm)
The DesignWare Mixed-Signal PHY IP for SATA and eSATA is designed for use in SoC solutions. The PHY integrates seamlessly with the DesignWare SATA AHCI Host digital controller to reduce design time and achieve first-pass silicon success. The SATA PHY provides a cost effective solution that is designed to meet the needs of today’s SATA designs. While extremely low in power consumption and area, the DesignWare SATA PHY substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity. The unique, advanced built-in diagnostics and sample automatic test equipment (ATE) test vectors available in the DesignWare PHY enable designers to implement complete at-speed production testing without expensive test equipment. Furthermore, the test vectors provide on-chip visibility into the actual link performance to quickly identify signal integrity issues.
The PHY includes a wide range of test capabilities including built-in per-channel BERTs, flexible fixed and random pattern generation, error counting on patterns or disparity, digital phase or voltage margining (bathtub curves), and built-in per channel scopes. The high-margin, robust SATA PHY architecture tolerates for manufacturing variations such as process, voltage and temperature. The SATA PHY passed interoperability testing utilizing industry-leading 65-nm, 40-nm, and 28-nm process technologies.
The PHY includes a wide range of test capabilities including built-in per-channel BERTs, flexible fixed and random pattern generation, error counting on patterns or disparity, digital phase or voltage margining (bathtub curves), and built-in per channel scopes. The high-margin, robust SATA PHY architecture tolerates for manufacturing variations such as process, voltage and temperature. The SATA PHY passed interoperability testing utilizing industry-leading 65-nm, 40-nm, and 28-nm process technologies.
Features
- Compliant with SATA/eSATA specification revision 3.3
- Excellent performance margin and receive sensitivity
- Very low power design; up to half the power compared to conventional PHYs
- Sample ATE test vectors provided for complete at-speed production testing
- Includes on-chip scope and built-in diagnostics for fast system verification
- Small, cost-effective die size
- Support for hot pluggable devices
- Optional spread-spectrum clock generation and absorption (SSC) with down-spread programmable from -5000ppm to -3000ppm
- Support for power down modes: partial, slumber and power down
Benefits
- Complete solution: Digital Controllers, PHY, and Verification IP
- Compliant with SATA/eSATA v3.3 and AHCI v1.3 specifications
- Compliant with SATA PIPE v4.3 specification
- Silicon-proven, shipping in volume
- Configurable ARM® AMBA®, AHB/AXI bus interfaces
- PHY optimized for low area and low power
- Controllers validated with Synopsys and third-party PHYs
- PHY and controller IP supports 1.5, 3 & 6 Gbps SATA operations
- Advanced built-in diagnostics for at-speed production testing
Applications
- Set-top box, DVD and digital TV
- Desktop and laptop
- Portable and network storage
- Hard disk, optical disk, flash, and solid state drives
- Enterprise and RAID storage systems
- Any system requiring a high-speed SATA host or device interface
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