The SATA Device IP Core incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The SATA Device IP Core is compliant with Serial ATA II specification and signaling rate is 1.5Gbps and scalable 3Gbs (6Gbs under way). The SATA Device IP Core is fully synchronous with system frequency (Clock_sys) at 37.5MHz in case of 1.5Gbps speed selection and 75MHz in case of 3Gbs speed selection. The source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.