HCLSATAHC26113G core handles data movement between system memory and a SATA device. The core implements transport layer & link layer functions.
HCLSATAHC26113G is fully compliant with SATA 2.6 specification and with the AHCI (Advanced Host Controller Interface) specification 1.1. The core supports both 1.5Gbps and 3Gbps data transfer rates.
The core has a flexible application/system bus interface and currently supports AMBA AHB interface. On the PHY side the core supports SAPIS/Vendor specific interface.
HCLSATAHC26113G implements flow control functions to offload CPU and handles automatic data transfer on the SATA interface.
- SATA Spec Rev2.6 compatible Link and Transport layer
- Supports 1.5Gbps and 3Gbps data rates
- Compliant to AHCI 1.1, support one port
- Supports Native Command Queuing (FPDMA)
- Supports ATAPI commands
- Supports power management functions
- Supports the DMA and PIO commands
- Supports speed negotiation
- Supports Far-end Retimed loopback
- Supports both Near-end & Far-end analog front-end loopback
- 32 bit FIFO-interface between Link layer and Transport layer
- Configurable TX and RX FIFOs
- DMA engine that compliance to AHCI register set
- Supports SAPIS interface at the PHY side (configurable)
- Configurable phy to link interface to 10 / 20 / 40 bits.
- AMBA AHB master/slave interface at the application
- 8b/10b coding on the link layer (option to disable the 8b/10b coding)
- CONT and data scrambling to reduce EMI
- Supports power management
- Supports Interrupt to Host processor
- Implements statistics counters (Optional)
- Supports OOB detection (COMWAKE, COMRESET/COMINIT)
- Source code – Verilog HDL
- Verification environment – C and Verilog
- Synopsys DC script
- User Manual
- Test case documents
- Coverage report