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Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
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SATA Host on Xilinx Zynq Artix 7
The LDS SATA 3 HOST XA7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Artix 7 speed grade 2 FPGA. The LDS SATA 3 HOST XA7 IP is compliant with Serial ATA III specification and signaling rate is fixed to 6Gbs. The LDS SATA 3 HOST XA7 IP is fully synchronous with system frequency (Clock_sys) at 75MHz in case of 3Gbs speed selection and 150MHz in case of 6Gbs speed selection. The source code format is available for ease of customization. The customization can be done by Logic Design Solutions and DO254 documentation is available on request.
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Block Diagram of the SATA Host on Xilinx Zynq Artix 7
