The so_ip_sata3_hctrl is a soft core implementation of SATA host controller as defined in the SATA Specification 3.2.
So-Logic's SATA-III Host Controller core is fully compliant with the SATA 3.2 specification, and supports both 1.5 Gbit/s, 3.0 Gbit/s and 6.0 Gbit/s data transfer rates.
SATA-III Host Controller core implements physical, link and transport layers. It can use both RocketIO GTP and GTX transceivers found in Xilinx FPGA devices to implement physical signaling required by the SATA specification. For the interface with the host processor IP core uses standard PATA interface, and for the interface with the DMA engine simple TX and RX transaction interface.
SATA-III Host Controller core is delivered with fully automated testbench and a complete set of tests allowing easy package validation at each stage of SoC design flow.
The design of SATA-III Host Controller core is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset. It operates at 37.5 MHz system clock frequency in case of SATA-I (1.5 Gbit/s data transfer rate), 75 MHz in case of SATA-II (3.0 Gbit/s data transfer rate) and at 150 MHz in case of SATA- III (6.0 Gbit/s data transfer rate) mode.
SATA-III Host Controller core can be evaluated using Xilinx FPGA Evaluation Platforms before purchase. This is achieved by using a time-limited demonstration bit file for Zynq-7000, Artix-7, Kintex-7, Virtax-7, Virtex-6 and Virtex-5 FPGA platforms that allows the user to connect it’s HDD to the SATA core and evaluate system performance under different transfer scenarios.
- Fully compliant with the Serial ATA specification revision 2.6
- Simple transaction interface with Host processor and DMA Engine
- 32-bit internal data path
- 8KB FIFO implemented by BlockRAM in both transmit and receive paths
- Low frequency operation
- IP Core system clock of 37.5MHz and PHY clock 75MHz for SATA-I
- IP Core system clock of 75.0MHz and PHY clock 150MHz for SATA-II
- Supports 1.5 Gbit/s and 3.0 Gbit/s data transfer rates
- Supports DMA and PIO commands
- Hardware support for Speed auto negotiation for SATA I/II
- 48-bit address set
- Detection of OOB, COMWAKE, K28.5, etc.
- 8b/10b coding and decoding
- CRC generation and checking
- Auto insertion of HOLD primitives
- Native Command Queuing (NCQ)
- Port Multiplier, Port Selector
- First Party DMA (FPDMA)
- CONT primitive support for primitive suppression to reduce EMI
- Implements the shadow register block and the serial ATA status and control registers
- Supports both Virtex5 FPGA GTP and GTX RocketIO Transceivers
- Reference design available on Zynq-7000, Artix-7, Kintex-7, Virtax-7, Virtex-6 and Virtex-5 Xilinx FPGA Evaluation Platfom
- Source code (source code license only)
- VHDL verification environment
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Instantiation templates
- Reference design
- Technical support
- IP Core implementation support
- Variable length maintenance
- Delivery of IP Core updates, minor and major changes
- Delivery of documentation updates
- Telephone & email support
- Hard Disk Drives (HDD)
- Solid State Drives (SDD)
- RAID controllers
- Data transfer and storage systems