SC9 Standard Cell Library - TSMC 40 nm CLN40G

Features

• Very large cell set to ensure optimal implementation of all types of design
• 1250 cells per Vt or channel length at 32/45 nm
• Smaller cell set in more mature technologies
• Wide variety of specialty cells like clock gating cells and decoupling capacitors
• Optimized cell set targeted performance range/applications
• Hand tuned and handcrafted cell designs for highest density and routeability
• Multiple beta (P:N) transistor ratios for performance - power tuning
• Tapless cell design for all libraries at 65nm and smaller geometries as well as for selected 180 to 90 nm libraries
• 65nm and larger geometries use M1 power rails
• 45nm and smaller geometries use M2 power rails for optimal support of restricted design rules
• Strain optimized layouts for high performance libraries in selected process nodes
• Leading edge design flow and model support
• CCS timing, noise and power, ECSM, Voltage Storm, Celtic and other specialty models
• Latest DRC rules and electrical models
• Extensive set of PVT corners
• Multi-Vdd Characterization
• Overdrive voltage support
• Support for temperature inversion corners
• High leakage corner (standard at 90 nm and below)
• Custom PVT support

Deliverables

• Front End (FE) and Back End (FB) views with full suite of design views and models that support most of the industry's popular design tools can be downloaded from the ARM DesignStart web site at: http://www.arm.com/support/designstart.php

• see the entire SC9 Standard Cell Library - TSMC 40 nm CLN40G datasheet
• get in contact with SC9 Standard Cell Library - TSMC 40 nm CLN40G Supplier