The DesignWare® SD/eMMC Host Controller IP addresses the growing storage needs of mobile, consumer, IoT and automotive applications. The IP provides advanced features such as ADMA3 for the SD 6.0, SDIO 4.10 specifications and Command Queuing Engine (CQE) for the SD 6.0 and eMMC 5.1 specifications. The IP also provides advanced high-performance 32- and 64-bit AXI interface to the system-on-chip (SoC). The IP architecture leverages power management techniques, making it ideal for low-power applications. The highly configurable and scalable IP is packaged with Synopsys coreConsultant tool and is optimized to reduce gate count and power consumption while ensuring compatibility with previous and future generation SD and eMMC specifications. A rigorous UVM-based verification methodology is applied to the DesignWare SD/ eMMC Host Controller IP, consisting of directed tests and constrained random verification. The simulation-based verification is further augmented with FPGA hardware verification based on Synopsys’ HAPS®-DX FPGA-based prototyping system. The FPGA development board is tested with all major SD cards, SDIO commands, and eMMC devices. The IP is in volume production and has been successfully implemented in a wide range of applications.