Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The operations necessary for the RSA cannot be efficiently implemented on an embedded CPU, typically requiring many seconds of the CPU time for signature verification.
RSA5X implements by far the most time-consuming operation of the RSA cryptography: so called “exponentiation” to enable low-power operation of the battery-powered devices.
RSA5X also can perform addition and multiplication in the GF(p) and GF(2n) Galois fields under microprogram control, allowing for flexible elliptic curve cryptography (ECC) calculation on arbitrary curves..
The design is fully synchronous and available in multiple configurations varying in bus widths and throughput.
- Small size: RSA5X starts from less than 15K ASIC gates (size greatly depends on the core configuration)
- Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications
- Support for RSA with programmable bit sizes
- Support for addition and multiplication in GF(p) and GF(2n) with programmable size
- Microprogramming support for elliptic curve algorithms
- Microprocessor-friendly interface using external dedicated memory for arguments, results, and scratch storage.
- An option to share the memory with the microprocessor is available.
- Test bench provided
- Synthesizable Verilog RTL source code
- Software modules for a complete RSA implementation (optional)
- Verilog testbench (self-checking)
- Software modules test harness
- Vectors for testbench and harness
- Expected results
- User Documentation
- Secure communications systems
- Digital Rights Management (DRM) for battery powered electronics
- Digital Signature using Reversible Public Key (rDSA) standard ANSI X9.31
- Digital Signature Standard (DSS) FIPS-186
- PKCS RSA cryptography per RFC 2347
- High performance RSA accelerators
- Elliptic curve cryptography per FIPS 186-3, NIST SP800-56A, SEC 1 and SEC 2 standards
Block Diagram of the Scalable RSA and Elliptic Curve Accelerator