1G/10G/25G/50G/100G Ethernet Switch IP Core - Efficient and Massively Customizable
Scalable Ultra-High Throughput DSC 1.2b Encoder
The core is designed for enabling ultra-high frame rate SD, HD and Ultra HD video encoding up to 10K resolutions, even in medium-end ASIC or FPGA silicon. The scalability of this IP core enables highly cost-effective silicon implementations of applications that need to handle massive pixel rates and resolutions. The UHT-DSC-E is available for ASIC or Intel, Lattice, Microsemi and Xilinx FPGA and SoC based designs.
The UHT-DSC-E is very easy to use and integrate in a system, designed for using only internal memory blocks and with simple, fully controllable and FIFO-like, streaming input and output interfaces. It requires minimal host intervention as it only needs to be programmed once per video sequence. Once programmed, it can encode an arbitrary number of video frames without the need of any further intervention or assistance by the host system CPU.
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Block Diagram of the Scalable Ultra-High Throughput DSC 1.2b Encoder

VESA DSC IP
- VESA DSC (Display Stream Compression) 1.2b Video Encoder
- VESA DSC (Display Stream Compression) 1.2b Video Decoder
- VESA DSC Encoder
- VESA Display Stream Compression (DSC) IP Core
- ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
- MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays