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RT-650 DPA-Resistant Hardware Root of Trust Security Processor for Govt/Aero/Defense FIPS-140
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SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
The eMMC 5.0 / SD3.0 Host Controller IP (3MCR) is a highly integrated host controller IP solution that supports three key memory and I/O technologies: SD, SDIO and eMMC memory formats. This IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
The eMMC 5.0 / SD3.0 Host Controller IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the IP.
The eMMC 5.0 / SD3.0 Host Controller IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the IP.
View SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller full description to...
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Block Diagram of the SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller IP Core
Video Demo of the SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller IP Core
Arasan eMMC 5.0 Host Controller Hardware Validation Platform Demonstration