SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
The eMMC 5.0 / SD3.0 Host Controller IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the IP.
Features
- Memory Card / Form Factors:
- SD Host Controller Spec v3.0* (SDXC)
- SDIO Spec v3.0
- SD Memory Spec v3.01
- eSD Memory Spec v2.1
- eMMC Spec v5.0
- IP Details:
- Built-in Master DMA for efficient data transfer
- Supports single slot
- SD - Secure Digital Memory Card
- 25/50/104/208 MHz
- 1,4 bit of data
- SDIO - SD Input/Output
- 25/50/104/208 MHz
- 1,4 bit of data
- eMMC -
- 26/52/208 MHz
- 1,4,8 bit of data
- HS200, HS400
Benefits
- Fully compliant core with proven silicon
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Unencrypted source code allows easy implementation
- Reuse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass
Deliverables
- RMM Compliant Synthesizable RTL design in Verilog
- Easy-to-use test environment
- Synthesis scripts
- Technical documents
Block Diagram of the SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller IP Core

Video Demo of the SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller IP Core
Arasan eMMC 5.0 Host Controller Hardware Validation Platform Demonstration
View SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller full description to...
- see the entire SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller datasheet
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