The SD 4.0 Device IP core is used to implement SD cards connected to a Host processor over standard SD bus. The flexible architecture of SD Device IP core is targeted to develop a range of memory cards.
The SD 4.0 Device IP core is fully compliant with the SD specification. It supports the dual row pin memory cards with D0+- and D1+- pins for differential signaling . Differential clock (RCLK) can be tuned in the range of 26Mhz to 52Mhz. It also supports SPI (Only SD3.0), SD1, and SD4 bit transfer modes, and multiple functions per card. High-speed and full speed
SD data transfers are also supported to capacities up to 2TB. All version 4.0 features are supported including the UHS-II PHY, SDHS, mini-SD, and micro SD extended 2.7-3.6V operating voltages. The SD Device controller includes a bidirectional FIFO that is expandable from 4 x 32-bit to any size required.
The SD 4.0 Device supports Half duplex(312 MB/s) and Full duplex(156 MB/s) in SD4.0 mode. It also supports low voltage and low power consumption with enhanced power management using new power Control mode by allowing LPS (Low power states like – EIDL and DORMANT)
The controller integrates a Scatter Gather DMA engine automating data transfers between the SD card and system memory.
The SD Device core is available with many system bus interfaces including AHB, AXI, OCP. The wide selection of interfaces enables the core to integrate effectively SOC designs today.