The Cadence® Host Controller IP for SD 4.0 UHS-I / eMMC 5.1 supports many features for low-power systems, including clock toggling disable. High-performance systems benefit from our advanced DMA engine (ADMA2) with scatter-gather operation. ADMA2 can read data from any number of different-sized locations within system memory without CPU interaction. For designs with silicon area constraints, we offer a single-operation DMA engine option, or you can choose to eliminate the DMA engine entirely.
The Host Controller IP for SD 4.0 UHS-I / eMMC 5.1 supports Default Speed, High Speed, and Ultra High Speed Phase I (SDR12, SDR25, SDR50, SDR104, DDR50) modes for SD/SDIO devices. It also supports Backward Compatible mode, High Speed SDR, and High-Speed DDR modes for eMMC devices.
The Controller IP for SD 4.0 UHS-I / eMMC 5.1 supports HS200 and HS400 high-speed modes for bandwidth of up to 400MB/s. In addition, the added Command Queuing Engine (CQE) improves smaller, random read-write operations, for higher system-level I/Os per second (IOPS).
- Supports SD memory, SD I/O cards, and eMMC devices
- Complies with SD Specification Version 4.0 (Host and PHY) and JEDEC eMMC Standard 4.41
- Supports Standard (SDSC), High (SDHC), and Extended (SDXC) capacity cards
- Supports Default Speed, High Speed and Ultra High Speed Phase I modes
- Features optional SDMA and ADMA2 modules
- Offers various system side interface options: ARM®AMBA®AHB, AMBA AXI
- Supports 1-bit, 4-bit, and 8-bit card buses
- Features ping-pong buffering with block size support up to 2048 bytes
- Features tuning/retuning logic of sample clock
- High bandwidth and low latency for best system performance
- Highly-integrated IP offering fast system integration and reduced design risk and cost
- Wide support of standards enables system flexibility for embedded and expandable storage
- Clean, readable, synthesizable Verilog RTL
- Synthesis scripts with SDC constraints file
- Verification testbench with test set
- Cloud computing
- Wireless communication equipment
- Mobile devices
- Consumer products
Block Diagram of the SD 4.0/eMMC 5.1 Host Controller IP Core