The Cadence® Host Controller IP for SD 4.0 UHS-I / eMMC 5.1 supports many features for low-power systems, including clock toggling disable. High-performance systems benefit from our advanced DMA engine (ADMA2) with scatter-gather operation. ADMA2 can read data from any number of different-sized locations within system memory without CPU interaction. For designs with silicon area constraints, we offer a single-operation DMA engine option, or you can choose to eliminate the DMA engine entirely.
The Host Controller IP for SD 4.0 UHS-I / eMMC 5.1 supports Default Speed, High Speed, and Ultra High Speed Phase I (SDR12, SDR25, SDR50, SDR104, DDR50) modes for SD/SDIO devices. It also supports Backward Compatible mode, High Speed SDR, and High-Speed DDR modes for eMMC devices.
The Controller IP for SD 4.0 UHS-I / eMMC 5.1 supports HS200 and HS400 high-speed modes for bandwidth of up to 400MB/s. In addition, the added Command Queuing Engine (CQE) improves smaller, random read-write operations, for higher system-level I/Os per second (IOPS).