The eMMC 5.0 / SD3.0 Host Controller IP (3MCR) is a highly integrated host controller IP solution that supports three key memory and I/O technologies: 1) SD, 2) SDIO and 3) eMMC memory formats. This IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the IP.
Arasan’s thorough verification methodology takes the risk out of integration of this functionality. As an Executive Member of the SD Association and JEDEC eMMC committee, Arasan is a leading provider of quality IP ensuring SoC designers risk-free integration of this advanced functionality. In addition to providing the Three Function MCR IP core, Arasan provides a family of different memory solutions to address a variety of needs. Arasan provides verification IP, test environment and a hardware development kit to ease integration into an SoC.