English
Real-time detector of zero-day attacks on processor - Cyber Escort Unit
You are here:
SDIO/SD Memory/MMC Slave Controller IP Core
The SDIO/SD Memory/MMC Slave Controller IP Core supports both 1 and 4 bit SD interface (up to 8 bits in optional MMC support) and SPI mode. Data rate of up to 25Mbyte/sec (200Mbs) can be realized with SD interface. Features such as plug and play, auto-detection, error correction, write protection are standard with SD card interface and are supported.
As a slave device, the SDIO/SD Memory/MMC Slave Controller IP Core receives commands from the host through the SD interface. Most of the commands are processed locally by the controller without any help from the user logic. The majority of the standard SD register set is also implemented within the slave controller and process by the core without help from the user logic.
In case of memory or IO access that needs to be forwarded to the user logic, the slave controller handles all the SD bus protocol and presents the request to the user logic as simple read and write request through parallel address and data buses. Burst transfer of up to 2048 bytes per transfer and user defined wait states are supported on the user interface to maximize data bandwidth. The slave controller also contains data buffer to match the speed differences between the user interface and the SD interface. It allows a much more efficient use of the user interface.
As a slave device, the SDIO/SD Memory/MMC Slave Controller IP Core receives commands from the host through the SD interface. Most of the commands are processed locally by the controller without any help from the user logic. The majority of the standard SD register set is also implemented within the slave controller and process by the core without help from the user logic.
In case of memory or IO access that needs to be forwarded to the user logic, the slave controller handles all the SD bus protocol and presents the request to the user logic as simple read and write request through parallel address and data buses. Burst transfer of up to 2048 bytes per transfer and user defined wait states are supported on the user interface to maximize data bandwidth. The slave controller also contains data buffer to match the speed differences between the user interface and the SD interface. It allows a much more efficient use of the user interface.
View SDIO/SD Memory/MMC Slave Controller full description to...
- see the entire SDIO/SD Memory/MMC Slave Controller datasheet
- get in contact with SDIO/SD Memory/MMC Slave Controller Supplier