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Perspective Transformation and Lens Correction Image Processor
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SDRAM DDR3/2 & LPDDR3/2 Hardened PHY - TSMC 65nm ULP
Dolphin s hardened DDRx SDRAM PHY and LPDDRx SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 2133 Mbps. It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).
In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin s DDRx and LPDDRx SDRAM Memory Controller IP.
In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin s DDRx and LPDDRx SDRAM Memory Controller IP.
Features
- + Dolphin DDR2/DDR3 PHY IP is fully compliant with the DFI 4.0 Specification
- + Support speeds of up to 2133Mbps with 1.8V oxide and 1600Mbps with 2.5V Oxide.
- + IP is split into 2 hard macros.
- + One for commands, control and address pins and another for 8-bit data bus.
- + Can support custom number of address bits.
- + Compensation controller and Pads are provided for automatic driver and receiver termination impedance calibration
- + Features include slew rate control, Per-bit de-skew, gate training, read and write leveling.
- + JTAG signals also provided for Mentor/Synopsys and LogicVision
- + Built in Self Test with a Pseudo Random Pattern Generator
- + Built with Scannable flops
- + Can be used in wirebond, flip-chip and cup configurations
Deliverables
- + Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
- + Synthesis and STA scripts
- + User guide documents
- + SV/UVM Verification suite with BFM
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sdram IP
- LPDDR4/3/2 DDR4/3/2 ComboPHY
- 32/64-bit PC133 SDRAM Controller
- Memory controller (SDRAM or DDR SDRAM)
- Memory controller (SDRAM or DDR SDRAM) and Arbiter
- DDR2 SDRAM Controller
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core