Perceptia’s DeepSub™ pPLL08 is a second-generation digital PLL providing the best jitter-power results in the industry. It achieves the lowest jitter or phase noise at a given power, or the lowest power at a given jitter or phase noise. It is capable of achieving extreme performance as required by the most demanding communication applications, including 5G base stations and handsets, Bluetooth LE, narrow-band IoT, SerDes, etc. It is suited for foundry processes of 40nm and below.
This hard IP includes a digitally-controlled LC-tank oscillator, which may have been optimized for the application. The second-generation architecture minimizes the need for mixed-signal circuits, and the signal loop is almost fully built with synthesized synchronous logic. Its only mixed-signal circuits are the digitally-controlled oscillator (DCO) and a part of the Phase Accumulator. This allows for accurate modeling of the PLL's behavior, and high predictability of its performance when ported to various process nodes. The use of digital circuits minimize influences of the process, voltage, and temperature (PVT) on the loop behavior. The design includes regulators and decoupling capacitors to reduce the influence of supply voltage noise.
The PLL loop filter is programmable, and its operation can be fully controlled via a control and status interface. The fractional-N operation is achieved with Perceptia proprietary and patented techniques, achieving high resolution at a low power. The fractional resolution is 24 bits. This allows control of the output frequency by better than 1/16th ppm relative to the internal reference clock frequency.
The PLL provides up to three outputs signals: one directly from the digitally-controlled oscillator (DCO), and two via separate post-scalers, which can each be bypassed by an auxiliary clock signal.
pPLL08 has a small footprint and integrates easily with other circuits.
- Fractional-N digital PLL architecture, using an LC-tank oscillator
- Ultra-low jitter and ultra-low phase noise, suitable for demanding wired, wireless and optical communications applications
- A prescaler R (divide by 1 to 7) on the reference clock input generates internal reference clock ck_ref
- Twenty-four bits fractional resolution
- Oscillator output frequency up to 8GHz
- Direct high-speed PLL output from the oscillator and two post-scalers with lower-speed outputs
- Configurable loop filter can be customized to optimize performance for specific crystals or reference clock sources. Supports loop bandwidths from sub-kHz to MHz.
- Lock-detect output
- Output duty cycle better than 48 / 52%
- Spread-spectrum clock (SSC) generation
- High noise immunity allows easy SoC integration
- The IP includes an internal regulator and supply decoupling
- Can be used without additional supply decoupling
- Highly testable using industry-standard flows
- ATPG vectors provided
- Specification of functional tests covering analog and custom-digital circuits
- Low power consumption
- Power-down modes cache the last state to enable accelerated lock on power-up
- Small footprint
- Industrial operating conditions (-40 to 85°C) with junction temperature up to 125°C.
- Timing/power models
- LEF5.6 abstract for floor planning/chip assembly
- Integration Guidelines
- GDSII layout macrocell
- CDL netlist (encrypted format) for LVS
- DRC, LVS and SI verification reports
- Verilog behavioral model and test bench
- ATPG model with accompanying documentation – allowing integration of the module in scan chains
- Functional test specification for tests that cannot be handled by ATPG vectors
- Characterization report
- Integration support
- 5G base station, 5G transceiver, 5G client
Block Diagram of the Second-Generation Digital Fractional-N PLL for 5G Applications