MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
Secure-IC's Securyzr(TM) TLS Handshake Hardware Accelerator
It combines a load dispatcher and a configurable amount of instances of the Public Key Crypto Engine (SCZ_IP_BA414EP) benefiting from all features supported (i.e. RSA/DH/DHE and ECDSA/ECDH/ECDHE/X.25519/X.448 and more). The efficient dispatching to several dozens of SCZ_IP_BA414EP instances helps reaching maximum system performance.
This IP is made of a core and optional modules to connect the core to standard interfaces (PCIe, AXI_DMA…). In addition our drivers have an asynchronous API (or non-blocking API) which are integrated in OpenSSL Async.
Implementation aspects
The TLS handshake hardware accelerator IP core is easily portable to ASIC and FPGA. It supports a wide range of applications on various technologies. The unique architecture offers a high level of scalability, enabling a trade-off between throughput, area and latency. For more detailed information about our Public Key Crypto Engine (SCZ_IP_BA414EP), please see our dedicated product sheet.
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