The SelectIO Interface Wizard is provided under the terms of the Xilinx End User License and is included with ISE and Vivado software at no additional charge.
Xilinx provides an easy to use wizard to configure the SelectIO blocks in Xilinx FPGAs.
The LogiCORE™ IP SelectIO™ Interface Wizard provides an intuitive customization GUI that helps users configure SelectIO blocks on Xilinx FPGAs to support their design requirements. The wizard generates an HDL wrapper that configures the SelectIO blocks such as IOSERDES and IODELAY and connects them to IO clock primitives in your design. Includes built-in templates to automate configuring of SelectIO to support various standard interfaces (SGMII, DVI, Camera Link, Chip to Chip) and a range of I/O signaling standards (LVCMOSxx, HSTLxx, SSTLxx).
- Supports input, output or bidirectional buses
- Simplifies the creation of clock circuitry to drive IO logic
- Supports data bus widths up to 32-bits wide
- Optional data serialization of up to 14 bits in DDR mode
- Optional data and/or clock delay insertion
- Single or double data rate data
- Single-ended or differential standards for clock and/or data
- Access to optional primitive ports
- Can be used with PlanAhead™ for additional IO configuration
- Implements optional Phase detector functionality
- Use the “auto-update” feature in CORE Generator to update the core to the latest version in your project.