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Single Port, Low Voltage, GLOBALFOUDNRIES 28 SLP, Low Leakage, Register File
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SerDes PHY IP in TSMC (7nm, 12/16nm, 28nm)
M31 SerDes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. The SerDes IP has supported data rates from 1.25G to 10.3125Gbps including XFI, SFI, 10GBASE-Kr, CEI, XAUI, USXGMII, QSGMII and SGMII. With the supports for both TX and RX equalization techniques, the SerRDes IP can meet the requirements for different channel conditions.
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SerDes IP
- 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- 250Mbps to 16Gbps Multiprotocol SerDes PMA
- 250Mbps to 8.1Gbps Multiprotocol SerDes Wirebond PMA
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP