Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s)

Features

• High Throughput: 531 MBytes/sec Read, 505 MBytes/sec Write
• Low Latency: 66K IOPS Read, 67K IOPS Write (4k blocks)
• Connects to SAPIS compliant serial ATA Phy
• Asynchronous, unrestricted SoC clock, independent of PHY clock
• Includes Xilinx Transceiver based PHY
• Fully compliant to SATA V3.0 COMPLIANCE CERTIFIED
• NCQ
• Port Multipliers
• Port Selector
• FIS based switching
• Supports Gen 1 (1.5 Gbps), Gen 2 (3.0 Gbps) and Gen 3 (6.0 Gbps)
• AXI Light interface for register access
• AXI Stream Interface and for data transfers
• Full support for PIO, DMA and FPDMA transfers
• 128 byte (32 double word) data FIFO (optional 256 byte)
• Implements the shadow register block and the serial ATA status and control registers
• Parallel ATA legacy software compatibility
• 48-bit address feature set supported
• 8b/10b coding and decoding
• CONT and data scramblers to reduce EMI
• CRC generation and checking
• Auto inserted HOLD primitives
• Power management support (partial and slumber)
• DMA Support
• Descriptor Based Command Processing
• Unlimited command list size
• Many configuration options
• ucLinux Drivers

Benefits

• High Performance
• AXI Interface
• Flexible
• Compact
• Cost-effective
• Many Shipping Products

Deliverables

• Verilog Source Code
• Test Bench
• Sample Synthesis scripts
• Documentation
• Reference Resign
• ucLinux Drivers

Applications

• Embedded Application
• ucLinux
• Data Recorder

Block Diagram of the Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s)

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