The SCI Slave is a synthesizable, flexible, and structured VHDL implementation of a Serial Controller Interface (SCI) that uses a two-wire bus for communicating between integrated circuits or standard peripherals like smart LCDs and keypads.
The SCI Slave complies with the definition of the ‘Inter-Integrated Circuit Bus’ (I2C). It is intended to be used as an interface block between the I2C buslines (SDA,SCL) and two mailbox memories. A local Mail-bus interface consisting of data, address and control lines allows you to interface registers or RAM’s up to a size of 256 bytes.
The SCI Slave contains the entire physical and data link layers, allowing to handle bus timing and frame generation/extraction, and thus reducing overhead from the system application.
- Slave Function
- 7-Bit Slave ID Address
- Automatic Incremented Address Pointer(AP)
- AP Initialization by transferring Word Address on I2C Bus
- Message Acknowledgement
- Customizable for Special Requirements
- iniSCI is modular structured into a BitSync bus interface, receiver, transmitter, and framer modules. This modular structure facilitates an understanding of the core’s functionality, thus simplifying customization.
- VHDL or Verilog RTL Source Code
- Functional Testbench
- Synthesys Script
- Data Sheet
- User Guide
- Hotline Support by means of phone, fax and e-mail
Block Diagram of the Serial Controller Interface IP Core