SGMII IP Phy is Serial Giga bit Media Independent Interface (SGMII) IP core and provides a single lane 1.25Gbps date rate interface to MAC layer and consists of Physical Convergent Sublayer (PCS) and Physical Media Dependent (PMD). SGMII IP transmitter includes Rate-Adaptation, Transmit state-machine and Serializer and transmitter IO blocks. The Receiver consists of Sampler, Clock Data Recovery (CDR) and high performance Phase-Lock Loop (PLL), Synchronization, Receive state-machine, and Rate adaptation blocks. The SGMII IP has a high performance rate Auto-negotiation block to negotiate rates between transmitter and receiver. The SGMII core is an ideal solution for applications requiring to connect the ASIC/SoC MAC to external 1000 BaseT Phy, where lowest power and pin counts is needed.